[PATCH] drm/amdgpu: unify gmc v10 and v11 get_vm_pde and get_vm_pte into common helpers
Andre Hirata
andrejhirata em usp.br
Sáb Abr 18 16:22:54 -03 2026
gmc_v10_0_get_vm_pde, gmc_v10_0_get_vm_pte and their v11 counterparts
are identical. Move the shared implementation to amdgpu_gmc.c as
amdgpu_gmc_get_vm_pde and amdgpu_gmc_get_vm_pte, and update both
gmc_v10_0 and gmc_v11_0 to use the common helpers to eliminate
code duplication.
No functional changes intended. BUG_ON preserved from original
gmc_v10_0 and gmc_v11_0 implementations.
Signed-off-by: Andre Hirata <andrejhirata em usp.br>
Co-developed-by: Gabriel Dimant <gabriel.dimant em usp.br>
Signed-off-by: Gabriel Dimant <gabriel.dimant em usp.br>
Co-developed-by: Guilherme Gabriel <guilhermesangabriel em usp.br>
Signed-off-by: Guilherme Gabriel <guilhermesangabriel em usp.br>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c | 75 +++++++++++++++
drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h | 7 ++
drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c | 119 +++++-------------------
drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c | 119 +++++-------------------
4 files changed, 130 insertions(+), 190 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
index 290b9f904..bdf54a992 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
@@ -1782,3 +1782,78 @@ int amdgpu_gmc_get_vram_info(struct amdgpu_device *adev,
}
return 0;
}
+
+/*
+ * Common get_vm_pde implementation for gmc v10 and v11.
+ */
+void amdgpu_gmc_get_nv_vm_pde(struct amdgpu_device *adev, int level,
+ uint64_t *addr, uint64_t *flags)
+{
+ if (!(*flags & AMDGPU_PDE_PTE) && !(*flags & AMDGPU_PTE_SYSTEM))
+ *addr = amdgpu_gmc_vram_mc2pa(adev, *addr);
+ BUG_ON(*addr & 0xFFFF00000000003FULL);
+
+ if (!adev->gmc.translate_further)
+ return;
+
+ if (level == AMDGPU_VM_PDB1) {
+ /* Set the block fragment size */
+ if (!(*flags & AMDGPU_PDE_PTE))
+ *flags |= AMDGPU_PDE_BFS(0x9);
+ } else if (level == AMDGPU_VM_PDB0) {
+ if (*flags & AMDGPU_PDE_PTE)
+ *flags &= ~AMDGPU_PDE_PTE;
+ else
+ *flags |= AMDGPU_PTE_TF;
+ }
+}
+
+/*
+ * Common get_vm_pte implementation for gmc v10 and v11.
+ */
+void amdgpu_gmc_get_nv_vm_pte(struct amdgpu_device *adev,
+ struct amdgpu_vm *vm,
+ struct amdgpu_bo *bo,
+ uint32_t vm_flags,
+ uint64_t *flags)
+{
+ if (vm_flags & AMDGPU_VM_PAGE_EXECUTABLE)
+ *flags |= AMDGPU_PTE_EXECUTABLE;
+ else
+ *flags &= ~AMDGPU_PTE_EXECUTABLE;
+
+ switch (vm_flags & AMDGPU_VM_MTYPE_MASK) {
+ case AMDGPU_VM_MTYPE_DEFAULT:
+ case AMDGPU_VM_MTYPE_NC:
+ default:
+ *flags = AMDGPU_PTE_MTYPE_NV10(*flags, MTYPE_NC);
+ break;
+ case AMDGPU_VM_MTYPE_WC:
+ *flags = AMDGPU_PTE_MTYPE_NV10(*flags, MTYPE_WC);
+ break;
+ case AMDGPU_VM_MTYPE_CC:
+ *flags = AMDGPU_PTE_MTYPE_NV10(*flags, MTYPE_CC);
+ break;
+ case AMDGPU_VM_MTYPE_UC:
+ *flags = AMDGPU_PTE_MTYPE_NV10(*flags, MTYPE_UC);
+ break;
+ }
+
+ if (vm_flags & AMDGPU_VM_PAGE_NOALLOC)
+ *flags |= AMDGPU_PTE_NOALLOC;
+ else
+ *flags &= ~AMDGPU_PTE_NOALLOC;
+
+ if (vm_flags & AMDGPU_VM_PAGE_PRT) {
+ *flags |= AMDGPU_PTE_PRT;
+ *flags |= AMDGPU_PTE_SNOOPED;
+ *flags |= AMDGPU_PTE_LOG;
+ *flags |= AMDGPU_PTE_SYSTEM;
+ *flags &= ~AMDGPU_PTE_VALID;
+ }
+
+ if (bo && bo->flags & (AMDGPU_GEM_CREATE_COHERENT |
+ AMDGPU_GEM_CREATE_EXT_COHERENT |
+ AMDGPU_GEM_CREATE_UNCACHED))
+ *flags = AMDGPU_PTE_MTYPE_NV10(*flags, MTYPE_UC);
+}
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h
index 6ab4c1e29..a852ed8ff 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h
@@ -484,4 +484,11 @@ void amdgpu_gmc_init_sw_mem_ranges(struct amdgpu_device *adev,
struct amdgpu_mem_partition_info *mem_ranges);
int amdgpu_gmc_get_vram_info(struct amdgpu_device *adev,
int *vram_width, int *vram_type, int *vram_vendor);
+void amdgpu_gmc_get_nv_vm_pde(struct amdgpu_device *adev, int level,
+ uint64_t *addr, uint64_t *flags);
+void amdgpu_gmc_get_nv_vm_pte(struct amdgpu_device *adev,
+ struct amdgpu_vm *vm,
+ struct amdgpu_bo *bo,
+ uint32_t vm_flags,
+ uint64_t *flags);
#endif
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
index e1ace7d44..129c7fc4b 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
@@ -418,6 +418,28 @@ static void gmc_v10_0_emit_pasid_mapping(struct amdgpu_ring *ring, unsigned int
amdgpu_ring_emit_wreg(ring, reg, pasid);
}
+static unsigned int gmc_v10_0_get_vbios_fb_size(struct amdgpu_device *adev)
+{
+ u32 d1vga_control = RREG32_SOC15(DCE, 0, mmD1VGA_CONTROL);
+ unsigned int size;
+
+ if (REG_GET_FIELD(d1vga_control, D1VGA_CONTROL, D1VGA_MODE_ENABLE)) {
+ size = AMDGPU_VBIOS_VGA_ALLOCATION;
+ } else {
+ u32 viewport;
+ u32 pitch;
+
+ viewport = RREG32_SOC15(DCE, 0, mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION);
+ pitch = RREG32_SOC15(DCE, 0, mmHUBPREQ0_DCSURF_SURFACE_PITCH);
+ size = (REG_GET_FIELD(viewport,
+ HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION, PRI_VIEWPORT_HEIGHT) *
+ REG_GET_FIELD(pitch, HUBPREQ0_DCSURF_SURFACE_PITCH, PITCH) *
+ 4);
+ }
+
+ return size;
+}
+
/*
* PTE format on NAVI 10:
* 63:59 reserved
@@ -450,106 +472,13 @@ static void gmc_v10_0_emit_pasid_mapping(struct amdgpu_ring *ring, unsigned int
* 1 system
* 0 valid
*/
-
-static void gmc_v10_0_get_vm_pde(struct amdgpu_device *adev, int level,
- uint64_t *addr, uint64_t *flags)
-{
- if (!(*flags & AMDGPU_PDE_PTE) && !(*flags & AMDGPU_PTE_SYSTEM))
- *addr = amdgpu_gmc_vram_mc2pa(adev, *addr);
- BUG_ON(*addr & 0xFFFF00000000003FULL);
-
- if (!adev->gmc.translate_further)
- return;
-
- if (level == AMDGPU_VM_PDB1) {
- /* Set the block fragment size */
- if (!(*flags & AMDGPU_PDE_PTE))
- *flags |= AMDGPU_PDE_BFS(0x9);
-
- } else if (level == AMDGPU_VM_PDB0) {
- if (*flags & AMDGPU_PDE_PTE)
- *flags &= ~AMDGPU_PDE_PTE;
- else
- *flags |= AMDGPU_PTE_TF;
- }
-}
-
-static void gmc_v10_0_get_vm_pte(struct amdgpu_device *adev,
- struct amdgpu_vm *vm,
- struct amdgpu_bo *bo,
- uint32_t vm_flags,
- uint64_t *flags)
-{
- if (vm_flags & AMDGPU_VM_PAGE_EXECUTABLE)
- *flags |= AMDGPU_PTE_EXECUTABLE;
- else
- *flags &= ~AMDGPU_PTE_EXECUTABLE;
-
- switch (vm_flags & AMDGPU_VM_MTYPE_MASK) {
- case AMDGPU_VM_MTYPE_DEFAULT:
- case AMDGPU_VM_MTYPE_NC:
- default:
- *flags = AMDGPU_PTE_MTYPE_NV10(*flags, MTYPE_NC);
- break;
- case AMDGPU_VM_MTYPE_WC:
- *flags = AMDGPU_PTE_MTYPE_NV10(*flags, MTYPE_WC);
- break;
- case AMDGPU_VM_MTYPE_CC:
- *flags = AMDGPU_PTE_MTYPE_NV10(*flags, MTYPE_CC);
- break;
- case AMDGPU_VM_MTYPE_UC:
- *flags = AMDGPU_PTE_MTYPE_NV10(*flags, MTYPE_UC);
- break;
- }
-
- if (vm_flags & AMDGPU_VM_PAGE_NOALLOC)
- *flags |= AMDGPU_PTE_NOALLOC;
- else
- *flags &= ~AMDGPU_PTE_NOALLOC;
-
- if (vm_flags & AMDGPU_VM_PAGE_PRT) {
- *flags |= AMDGPU_PTE_PRT;
- *flags |= AMDGPU_PTE_SNOOPED;
- *flags |= AMDGPU_PTE_LOG;
- *flags |= AMDGPU_PTE_SYSTEM;
- *flags &= ~AMDGPU_PTE_VALID;
- }
-
- if (bo && bo->flags & (AMDGPU_GEM_CREATE_COHERENT |
- AMDGPU_GEM_CREATE_EXT_COHERENT |
- AMDGPU_GEM_CREATE_UNCACHED))
- *flags = AMDGPU_PTE_MTYPE_NV10(*flags, MTYPE_UC);
-}
-
-static unsigned int gmc_v10_0_get_vbios_fb_size(struct amdgpu_device *adev)
-{
- u32 d1vga_control = RREG32_SOC15(DCE, 0, mmD1VGA_CONTROL);
- unsigned int size;
-
- if (REG_GET_FIELD(d1vga_control, D1VGA_CONTROL, D1VGA_MODE_ENABLE)) {
- size = AMDGPU_VBIOS_VGA_ALLOCATION;
- } else {
- u32 viewport;
- u32 pitch;
-
- viewport = RREG32_SOC15(DCE, 0, mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION);
- pitch = RREG32_SOC15(DCE, 0, mmHUBPREQ0_DCSURF_SURFACE_PITCH);
- size = (REG_GET_FIELD(viewport,
- HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION, PRI_VIEWPORT_HEIGHT) *
- REG_GET_FIELD(pitch, HUBPREQ0_DCSURF_SURFACE_PITCH, PITCH) *
- 4);
- }
-
- return size;
-}
-
static const struct amdgpu_gmc_funcs gmc_v10_0_gmc_funcs = {
.flush_gpu_tlb = gmc_v10_0_flush_gpu_tlb,
.flush_gpu_tlb_pasid = gmc_v10_0_flush_gpu_tlb_pasid,
.emit_flush_gpu_tlb = gmc_v10_0_emit_flush_gpu_tlb,
.emit_pasid_mapping = gmc_v10_0_emit_pasid_mapping,
- .get_vm_pde = gmc_v10_0_get_vm_pde,
- .get_vm_pte = gmc_v10_0_get_vm_pte,
+ .get_vm_pde = amdgpu_gmc_get_nv_vm_pde,
+ .get_vm_pte = amdgpu_gmc_get_nv_vm_pte,
.get_vbios_fb_size = gmc_v10_0_get_vbios_fb_size,
};
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c
index 94d6631ce..f1ac292b8 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c
@@ -410,6 +410,28 @@ static void gmc_v11_0_emit_pasid_mapping(struct amdgpu_ring *ring, unsigned int
amdgpu_ring_emit_wreg(ring, reg, pasid);
}
+static unsigned int gmc_v11_0_get_vbios_fb_size(struct amdgpu_device *adev)
+{
+ u32 d1vga_control = RREG32_SOC15(DCE, 0, regD1VGA_CONTROL);
+ unsigned int size;
+
+ if (REG_GET_FIELD(d1vga_control, D1VGA_CONTROL, D1VGA_MODE_ENABLE)) {
+ size = AMDGPU_VBIOS_VGA_ALLOCATION;
+ } else {
+ u32 viewport;
+ u32 pitch;
+
+ viewport = RREG32_SOC15(DCE, 0, regHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION);
+ pitch = RREG32_SOC15(DCE, 0, regHUBPREQ0_DCSURF_SURFACE_PITCH);
+ size = (REG_GET_FIELD(viewport,
+ HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION, PRI_VIEWPORT_HEIGHT) *
+ REG_GET_FIELD(pitch, HUBPREQ0_DCSURF_SURFACE_PITCH, PITCH) *
+ 4);
+ }
+
+ return size;
+}
+
/*
* PTE format:
* 63:59 reserved
@@ -441,106 +463,13 @@ static void gmc_v11_0_emit_pasid_mapping(struct amdgpu_ring *ring, unsigned int
* 1 system
* 0 valid
*/
-
-static void gmc_v11_0_get_vm_pde(struct amdgpu_device *adev, int level,
- uint64_t *addr, uint64_t *flags)
-{
- if (!(*flags & AMDGPU_PDE_PTE) && !(*flags & AMDGPU_PTE_SYSTEM))
- *addr = amdgpu_gmc_vram_mc2pa(adev, *addr);
- BUG_ON(*addr & 0xFFFF00000000003FULL);
-
- if (!adev->gmc.translate_further)
- return;
-
- if (level == AMDGPU_VM_PDB1) {
- /* Set the block fragment size */
- if (!(*flags & AMDGPU_PDE_PTE))
- *flags |= AMDGPU_PDE_BFS(0x9);
-
- } else if (level == AMDGPU_VM_PDB0) {
- if (*flags & AMDGPU_PDE_PTE)
- *flags &= ~AMDGPU_PDE_PTE;
- else
- *flags |= AMDGPU_PTE_TF;
- }
-}
-
-static void gmc_v11_0_get_vm_pte(struct amdgpu_device *adev,
- struct amdgpu_vm *vm,
- struct amdgpu_bo *bo,
- uint32_t vm_flags,
- uint64_t *flags)
-{
- if (vm_flags & AMDGPU_VM_PAGE_EXECUTABLE)
- *flags |= AMDGPU_PTE_EXECUTABLE;
- else
- *flags &= ~AMDGPU_PTE_EXECUTABLE;
-
- switch (vm_flags & AMDGPU_VM_MTYPE_MASK) {
- case AMDGPU_VM_MTYPE_DEFAULT:
- case AMDGPU_VM_MTYPE_NC:
- default:
- *flags = AMDGPU_PTE_MTYPE_NV10(*flags, MTYPE_NC);
- break;
- case AMDGPU_VM_MTYPE_WC:
- *flags = AMDGPU_PTE_MTYPE_NV10(*flags, MTYPE_WC);
- break;
- case AMDGPU_VM_MTYPE_CC:
- *flags = AMDGPU_PTE_MTYPE_NV10(*flags, MTYPE_CC);
- break;
- case AMDGPU_VM_MTYPE_UC:
- *flags = AMDGPU_PTE_MTYPE_NV10(*flags, MTYPE_UC);
- break;
- }
-
- if (vm_flags & AMDGPU_VM_PAGE_NOALLOC)
- *flags |= AMDGPU_PTE_NOALLOC;
- else
- *flags &= ~AMDGPU_PTE_NOALLOC;
-
- if (vm_flags & AMDGPU_VM_PAGE_PRT) {
- *flags |= AMDGPU_PTE_PRT;
- *flags |= AMDGPU_PTE_SNOOPED;
- *flags |= AMDGPU_PTE_LOG;
- *flags |= AMDGPU_PTE_SYSTEM;
- *flags &= ~AMDGPU_PTE_VALID;
- }
-
- if (bo && bo->flags & (AMDGPU_GEM_CREATE_COHERENT |
- AMDGPU_GEM_CREATE_EXT_COHERENT |
- AMDGPU_GEM_CREATE_UNCACHED))
- *flags = AMDGPU_PTE_MTYPE_NV10(*flags, MTYPE_UC);
-}
-
-static unsigned int gmc_v11_0_get_vbios_fb_size(struct amdgpu_device *adev)
-{
- u32 d1vga_control = RREG32_SOC15(DCE, 0, regD1VGA_CONTROL);
- unsigned int size;
-
- if (REG_GET_FIELD(d1vga_control, D1VGA_CONTROL, D1VGA_MODE_ENABLE)) {
- size = AMDGPU_VBIOS_VGA_ALLOCATION;
- } else {
- u32 viewport;
- u32 pitch;
-
- viewport = RREG32_SOC15(DCE, 0, regHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION);
- pitch = RREG32_SOC15(DCE, 0, regHUBPREQ0_DCSURF_SURFACE_PITCH);
- size = (REG_GET_FIELD(viewport,
- HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION, PRI_VIEWPORT_HEIGHT) *
- REG_GET_FIELD(pitch, HUBPREQ0_DCSURF_SURFACE_PITCH, PITCH) *
- 4);
- }
-
- return size;
-}
-
static const struct amdgpu_gmc_funcs gmc_v11_0_gmc_funcs = {
.flush_gpu_tlb = gmc_v11_0_flush_gpu_tlb,
.flush_gpu_tlb_pasid = gmc_v11_0_flush_gpu_tlb_pasid,
.emit_flush_gpu_tlb = gmc_v11_0_emit_flush_gpu_tlb,
.emit_pasid_mapping = gmc_v11_0_emit_pasid_mapping,
- .get_vm_pde = gmc_v11_0_get_vm_pde,
- .get_vm_pte = gmc_v11_0_get_vm_pte,
+ .get_vm_pde = amdgpu_gmc_get_nv_vm_pde,
+ .get_vm_pte = amdgpu_gmc_get_nv_vm_pte,
.get_vbios_fb_size = gmc_v11_0_get_vbios_fb_size,
};
--
2.43.0
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